SOI transistor for high speed devices
and satellite applications.

Onno W. Purbo

Department of Electrical and Computer Engineering
University of Waterloo
Waterloo, Ontario
Canada N2L 3G1

on leave from:
Department of Electrical Engineering
Institute of Technology Bandung
INDONESIA

Inter University Center on Microelectronics
Institute of Technology Bandung
INDONESIA

ABSTRACT

		Dalam paper ini, usaha untuk membuat polysilikon emitter bipolar transistor pada Silicon-on-Insulator (SOI) wafer akan dilaporkan. Perbandingan antara transistor yang dibuat pada Silicon and SOI wafer akan dilakukan. Beberapa perbedaan karakteristik kami amati pada transistor ini. Akhirnya, kemungkinan untuk mengadopsi teknologi ini di Indonesia akan dibahas.

		Polysilicon emitter bipolar transistors have been successfully fabricated on Silicon-on-Insulator (Zone-Melting-Recrystallization) wafer. Comparisons between transistors fabricated on Silicon and SOI wafers are performed and are found to have some characteristics differences. These differences include higher emitter resistances, higher collector resistance and higher current gain for SOI transistors. Possibilities to adopt this technology in Indonesia will be reviewed.

INTRODUCTION.

	The use of buried oxide layer in Silicon-on-Insulator (SOI) technology offers many advantages. Same process as bulk-Silicon may be directly adapted in SOI technology and, yet, yields faster circuits [1]. The only difference may be in a simplified dielectric isolation process [2]. Reduced collector-substrate capacitance due to buried oxide layer may give 10-12% increase in ECL gate delay [1]. Simplified dielectric isolation process yields complete device isolation. This in turn will minimize capacitive coupling between various circuit elements as well as eliminate latch-up path (in CMOS circuits). In addition, the use of dielectric isolation reduces isolation area and, thus, improves packing density which results-in smaller chip size. Simpler process and greater flexibility in circuit design and layout, e.g., easier to obtain BiCMOS devices [3], leads to lower chip costs.
	Despite of the advantages of SOI technology, only few work have been done on bipolar transistors on SOI wafers. Some of these work have been summarized in Table 1. As shown most of the early work [3,4] are in lateral bipolar transistors (sometimes merge with MOSFET). In lateral structures, it is difficult to realize polysilicon emitter transistor. Although with ungainly extra steps, it can be in principle be done. Most of the vertical transistors on SOI [5-9] are metal contacted emitter. Vertical Polysilicon Emitter Transistor (PET) offers self-aligned, reduced area and, thus, increased transistor's speed [1]. SIMOX [10] and BESOI [1] wafers have been used to fabricate polysilicon emitter transistors. Most of them use implant process to create the base and emitter, only Munzel et.al. [7] uses double-diffuse process. The highest gain of SOI bipolar transistors reported so far is 100. Three different logic families, i.e., BiCMOS, ECL and TTL, have been fabricated. Circuits on SOI wafers are usually faster than that the bulk-Silicon [6,10].
	In this paper, we report on our attempt to fabricate vertical PETs on Zone-Melting-Recrystallization (ZMR) SOI wafers. Current gain as high as 230 is obtained. Comparisons will be made to the PETs on bulk-Silicon with the same process. Finally, the possibilities to adopt SOI technology in Indonesia will be explored.

EXPERIMENTAL RESULTS.

	ZMR wafers and 3 micron epi thickness (n-n+) bulk-Silicon wafers with nominal doping density of 1016 cm-3 are used as our starting materials. Two inch diameter bulk-Silicon wafers and one inch square ZMR wafers are used. The buried layer in ZMR wafer is formed by Arsenic implantation with dose of 3.7 x 1014 cm-2 at 60 keV. Subsequently, 1.5 micron n-type epitaxial layer with nominal doping density of 1016 cm-3 is deposited. Transistor base is formed by Boron implantation with dose of 1013 cm-2 at 20 keV. After deposit 0.1 micron oxide layer, emitter window is opened. HF-dip etch is used prior to 0.3 micron undoped-polysilicon deposition. Arsenic implant with dose 2 x 1016 cm-2 at 120 keV is used to create the n+ emitter. Annealing and drive-in process is performed at 900oC for 30 minutes in dry O2 and 4 minutes in N2. After metal deposition and contact formation, annealing at 250oC in N2 and H2 ambient gas is performed for 30 minutes to improve the current-voltage characteristics. Except buried layer and epitaxial layer, both ZMR and bulk-Silicon received the same process. Junction depth about 0.02 micron and 0.2 micron for emitter and base, respectively, is predicted by SUPREM. The final structure of the transistors is shown in Fig. 1.
	Measurement is performed on our double base contact 7 x 7 μm2 emitter PETs using HP4145A Semiconductor Parameter Analyzer. We found that the transistor's current-voltage characteristics are repeatable from one chip to another. However, lower carrier life-time and higher defect density in ZMR wafers [11] may give some problems that may lead to device failure and, thus, lower yield.
	The measured data for PETs on SOI and bulk-Silicon wafers are tabulated in Table 2. We found that the total wafer yield of SOI process is lower than that bulk-Silicon process as expected. We also observed different the failure mode in SOI and bulk-Silicon bipolar transistors. In spite of thinner epitaxial layer in our SOI wafers, the collector breakdown voltage and the collector saturation current are approximately the same for both wafer types. The collector resistance of SOI PETs is higher. In addition, the Early voltage of SOI PETs is lower than that bulk-Silicon.
	Figure 2. shows the Gummel plot of SOI PETs (dashed-lines) and bulk-Silicon PETs (solid-lines). It is interesting to note that the collector current is overlapping one on top the other indicating the same Gummel number. However, the base current of SOI PETs is lower than that bulk-Silicon PETs. This may be possible if the minority carrier penetration from the base into the emitter is decreased. The lower minority base current leads to higher SOI PETs current gain.
	Open collector method shows higher emitter resistance for SOI PETs. Higher emitter resistance as well as lower base current for the same Vbe in SOI PETs may be due to thicker interfacial oxide layer between polysilicon and bulk-Silicon emitter. The ability of minority carrier to penetrate the emitter will be decreased due to the thicker interfacial oxide. In addition, this may lead to a conclusion that the surface properties of bulk-Silicon wafers and epitaxially deposited SOI wafers are different. The lower Early voltage may be due to shorter base width and, thus, different diffusivity of boron or arsenic in epitaxial layer grown on SOI and bulk-Silicon. The discrepancies between PETs fabricated on bulk-Silicon and SOI wafers may need to be further verified, e.g., using SIMS and Spreading Resistance analysis. This may include the effects of high defect density and crystal misorientation in the ZMR wafer to the quality of the deposited-epitaxial layer as well as the polysilicon-epitaxial interface properties in Polysilicon emitter transistor.

POSSIBILITIES TO ADOPT SOI TECHNOLOGY IN INDONESIA

	As far as the microelectronics processing facilities are concerned, the major problems in adopting this technology is in the use of ion implantation process to from very shallow n or p type structure. The rest of the process is involving basically annealing, oxidation, polysilicon deposition and window opening processes. The basic microelectronics processing facilities at Inter University Center (IUC) on Microelectronics in Indonesia are located in class 1000 and 10.000 clean rooms. It is currently capable to perform most of these processes. PUSLITBANG TEKOMA-LIPI in Indonesia is currently installing and trying to run their ion implantation facilities. Thus, it is just a matter of time, the microelectronics facilities will be established and ready to run and to adopt the SOI technology [13].
	Despite the advancement of the microelectronics facilities in Indonesia, human factors will play the most important role in moving the technology forward. The man-power needed to back-up the microelectronics development is currently being prepared. Several Indonesian Ph.D candidates in microelectronics area will be finishing their program in Western Universities in the next one or two years. Information network for microelectronics collaboration is being developed. Hopefully, the infra-structure needed to aid the microelectronics development in Indonesia will be established in the next 5-10 years.

SUMMARY

	We have successfully fabricated polysilicon emitter transistors on Zone-Melting-Recrystallized SOI wafers. The resulting transistor's characteristics on the same wafer is highly repeatable from one chip to another. The transistors fabricated on SOI wafer have lower yield, higher collector resistance, higher current gain and about the same breakdown voltage with respect to similar transistor fabricated on bulk-Silicon. Improvement in current-voltage characteristics may be obtained by performing low temperature annealing after metal deposition. There are open questions to be investigated on the SOI material properties and its effects to vertical bipolar transistor's performance.

ACKNOWLEDGEMENT

The author wishes to thank the government of Indonesia for granting the overseas scholarship.

REFERENCES

[1]	K. Ueno, M. Kawano, and Y. Arimoto, "High-speed radiation hardened ECL circuits on bonded SOI wafers," Proceedings ESSDERC '90, pp. 377-380, 1990.

[2]	B.Y. Tsaur, "Zone-melting-recrystallization Silicon-on-Insulator technology," IEEE Circuits and Devices Mag., pp. 12-16, June 1987.

[3]	B.Y. Tsaur, D.J. Silversmith, J.C.C. Fan, and R.W. Mountain, "Fully isolated lateral bipolar - MOS transistors fabricated in zone-melting recrystallized Si films on SiO2," IEEE Electron Device Lett., Vol. EDL-4, No. 8, pp. 269-271, 1983.

[4]	M. Rodder and D.A. Antoniadis, "Silicon-on-insulator bipolar transistors," IEEE Electron Device Lett., Vol. EDL-4, No. 6, pp. 193-195, 1983.

[5]	E.W. Greeneich and R.H. Reuss, "Vertical n‑p‑n bipolar transistors fabricated on buried oxide SOI," IEEE Electron Device Lett., Vol. EDL‑5, No. 3, pp. 91‑93, 1984.

[6]	D.G. Platteter and T.F. Cheek, Jr., "The use of multiple implants for fabrication of bipolar Silicon-on-Insulator integrated circuits," IEEE Trans. Nuc. Sci., Vol. 35, No. 6, pp. 1350-1354, 1988.

[7]	H. Munzel, G. Albert, and H. Strack, "Vertical bipolar transistors on buried Silicon Nitride layers," IEEE Electron Device Lett., Vol. EDL‑5, No. 7, pp. 283‑285, 1984.

[8]	B.Y. Tsaur, R.W. Mountain, C.K. Chen, and J.C.C. Fan, "Merged CMOS/bipolar technologies utilizing zone‑melting‑recrystallized SOI films," IEEE Electron Device Lett., Vol. EDL‑5, No. 11, pp. 461‑463, 1984.

[9]	J.C. Sturm and J.F. Gibbons, "Vertical bipolar transistors in laser-recrystallized polysilicon," IEEE Electron Device Lett., Vol. EDL-6, No. 8, pp. 400-402, 1985.

[10]	S. Matsumoto, T. Ohno, and K. Izumi, "study on BiCMOS devices utilizing SIMOX technology," Electron. Lett., Vol. 25, No. 14, pp. 904-905, 1989.

[11]	T.D. Stanley and P.K. Vasudev, "Recent advances in Silicon-on-Insulator technologies," Solid-State Technology, Vol. 33, No. 11, p. 48, 1990.

[12]	J.C. Sturm, J.P. McVittie, J.F Gibbons, and L. Pfeiffer, "A lateral Silicon‑on‑Insulator bipolar transistor with a self‑aligned base contact," IEEE Electron Device Lett., Vol. EDL‑8, No. 3, pp. 104‑106, 1987.

[13]	Onno W. Purbo, "Teknologi Mikroelektronika untuk satelit Palapa," KOMPAS January 1991.

FIGURE CAPTIONS

Figure 1.	Cross-sectional view of Polysilicon emitter bipolar transistor fabricated on Zone-Melting-Recrystallized (ZMR) wafers.

Figure 2.	Gummel plots of Polysilicon emitter transistors (PETs) after 250oC annealing for 30 minutes. Dashed-lines are PETs fabricated on ZMR wafers. While solid-lines are PETs on bulk-Silicon. The base current of the PETs on SOI is notably lower than that on bulk-Silicon.

Table 1. Reported Bipolar Transistors on SOI wafers.

type	SOI	BL	PET	ref	yr	gain	logic	
L	ZMR	N	N	[3,4]	83	2.5-18	-	
V	SIMOX	N	N	[5]	84	-	-	
V	ZMR	Y&N	N	[8]	84	100	BiCMOS	
V	SIMNI	N	N	[7]	84	100	-	
V	laser recrys.	N	N	[9]	85	20-40	-	
L	ZMR	N	N	[12]	87	10-50	-	
V	SIMOX	Y	N	[6]	88	100	TTL	
V	SIMOX	Y	Y	[10]	89	-	BiCMOS	
V	BESOI	Y	Y	[1]	90	-	ECL	
		BL. = buried layer.   V = vertical.   L = lateral.

Table 2. Measured PETs on SOI and bulk-Silicon wafers.

parameters	ZMR	bulk-Silicon	
hFE	230	150	
Vcbr (Volt)	23	26	
Ico (A)	10-8	10-8	
Rc (ohm)	300	150	
Re (ohm)	100	27	
Early Voltage (v)	17	27	
total yield	(50/121) 41.3%	148/238 (62.2%)	

Figure 1.	Cross-sectional view of Polysilicon emitter bipolar transistor fabricated on Zone-Melting-Recrystallized (ZMR) wafers.

Figure 2.	Gummel plots of Polysilicon emitter transistors (PETs) after 250oC annealing for 30 minutes. Dashed-lines are PETs fabricated on ZMR wafers. While solid-lines are PETs on bulk-Silicon. The base current of the PETs on SOI is notably lower than that on bulk-Silicon.